1. Field of the Invention
The present invention relates to a method for programming multilevel memories and to a corresponding circuit and, more specifically, to a method for programming multilevel memories of the flash EEPROM type wherein the memory comprises a matrix of cells organized in rows and columns and grouped in memory words and to a circuit of the above type for NROM flash memories with two-bit cells.
2. Description of the Related Art
As is well known in semiconductor-integrated memory electronic devices the need for greater “density” has led to the development of so-called multilevel memories, i.e., memories wherein each single flash cell stores a number of bits greater than one.
A fundamental operation in multilevel memories is programming. In fact, in the case of multilevel memories, with respect to the programming of single-level memories, it is necessary to control, in a very accurate way, the threshold voltage values of the multilevel cells.
A first known solution to meet this need is represented by a multilevel programming method that uses a sequence of programming and verification pulses.
Making reference, by way of non limiting example, to a memory with two bits per cell, if the distribution of the cells “00” is considered as a single-level distribution, the method can be divided in two steps: a first real multilevel step, used for constructing the distributions “10” and “01” and a subsequent quicker step for constructing the distribution “00”. It should be noted that the programming of the cells “00” does not necessarily require continuously verifying the evolution of the threshold of the cells under programming.
In a classical multilevel programming method, a programming step involves a series of box-like voltage pulses applied to the gate terminal of the cells to be programmed, alternated by verify operations. The width of the programmed distribution is a function of the voltage difference between two successive pulses and of the precision with which the cell terminals are regulated. In general, a precise regulation of the voltage implies a slowness of the regulation itself. The verify and programming operations require two different voltage levels applied to the gate terminal.
FIG. 1 shows the drain (Vdrain) and gate (Vgate) voltages of a memory cell during a multilevel programming. The gate voltage (Vgate) switches between different values, for controlling the programming and verify operations of a cell, employing a time Tpvi for switching from a programming voltage value (Vgi 1=1 . . . N) to a verify voltage value (Vv) and a time Tvpi for performing the contrary switch.
The programming Vgi and verify Vv voltage values are obtained by the same charge pump circuit.
FIG. 2, by way of example, globally and schematically shows a programming circuit 100 of a multilevel memory cell.
In the circuit there are a first supply block 1, including, for example, a charge pump 1a, intended to supply voltage values for programming and verify operations and a second supply block 2 that has a charge pump 2a intended to supply voltage values for read operations of memory cells. The charge pump 1a has a first output line Umod, whereas the second charge pump 2a has an output line Uread.
A voltage Vxs that is regulated by the two charge pumps 1a, 2a is brought, through a switch 4, to the input of a row decoder 3, in turn connected to word lines WLs of the multilevel memory. The switch 4 selects the operation which is to be performed on a corresponding multilevel memory cell, i.e., programming, verifying and reading.
The switch 4 has a voltage elevator or booster 5 that includes an input connected to a logic gate 6 in turn receiving at an input an enable signal SECT_EN and an operative mode signal MOD. The signal SECT_EN enables a sector whereon an operation has to be performed, whereas the operative mode signal MOD identifies the operation which is to be performed, i.e., programming, verifying or reading.
Although advantageous under several aspects, this multilevel programming method shows various drawbacks.
In particular, the management, by a single supply block 1 and, in particular by the single charge pump 1a, of the switches of the voltage Vxs on the word line WLs, from a programming voltage level to the verify one and vice versa requires considerable time.
The circuit 100, by means of the charge pump 1a, increases the voltage Vxs for a successive programming pulse of a cell only after the end of a verify operation; in consequence, before emitting a new pulse a long time Tvpi will transpire. Moreover, the time required also increases when the absolute value of the difference between the verify voltage and the voltage of the pulse produced by the charge pump 1a voltage increases, as shown in FIG. 1 wherein Tvpi>Tvpi+1 and Tvpi>Tvpi+1. In consequence, the management of the switches tends to become slower and slower.
The technical problem underlying the present invention is that of providing a multilevel programming method having such functional characteristics that reduces the programming times of multilevel cells, overcoming the limits and the drawbacks affecting the known methods.